This invention relates to microminiature integrated-circuit devices and, more particularly, to a method for forming conductive plugs in vias in very-large-scale-integrated (VLSI) devices.
The problem of conductively filling vias in dielectric layers of VLSI devices is frequently an extremely difficult one. This is especially so if the vias have vertical or near-vertical walls and an aspect (or height-to-diameter) ratio that exceeds unity. For such vias, conventional techniques such as sputtering of aluminum typically exhibit poor step-coverage and/or other properties which make them unsatisfactory in practice for inclusion in fabrication sequences for making VLSI devices.
Accordingly, workers in the art have directed considerable efforts at trying to devise improved ways of conductively filling vias. It was recognized that these efforts if successful could be an important factor in improving the yield and lowering the cost of VLSI devices.